1. Field
The present invention relates to interface circuits, and more particularly to an interface circuit for providing signal level translation between an emitter coupled logic circuit, hereafter referred to as ECL, and a transistor-transistor logic circuit, hereafter referred to as TTL.
2. Background
Historically in the field of semiconductor integrated circuits, ECL has not been favored for small numbers of circuit functions because of the requirement to provide a reference voltage, usually designated V.sub.BB, plus at least one current source for each function. However as the requirement for increased speed in circuit applications has continued, the benefits of ECL, which is inherently a faster, lower power consuming logic system, have been more attractive in those applications where reference voltages and current sources can be provided without undue economic burden. Such a situation exists in integrated circuit bipolar memory where high speed access times and low power consumption are required. In such an application a common reference voltage, V.sub.BB, and a common current sourcing system can be provided to the entire memory array, memory address decoders and associated memory control circuits. Here, ECL can be implemented without undue economic burden.
While ECL logic is favored for certain logic functions, as described above, because of logic efficiency and other considerations not available in TTL, TTL logic is favored for certain other logic functions, gates and output driving means. Hence, it is desirable to design integrated bipolar memory such that the internal circuitry is of the higher performance ECL type while the input and output circuits are logic level compatible with the TTL logic form.
Previously, conversion of the internal ECL logic signals to TTL signals at the output has been accomplished with resistors and zener diodes. Additionally, some schemes using multiple stages of transistor amplification in series have been devised. All of these approaches significantly increase the total memory circuit access time which is undesirable and, to a great extent, reduce the advantage of using internal ECL circuitry. In some of these cases, translation schemes requiring more than one power supply voltage have been used. It is a highly desirable to use only one power supply to support both the internal ECL and the TTL interface circuits.
To do with one supply, zener diodes are unsatisfactory because the reference voltage, V.sub.BB, of ECL is not fixed in an absolute sense but may vary in a system. Furthermore, the voltage drop across zener diodes is usually too high, and zener diodes provide a fixed voltage drop which cannot be used to satisfactorily achieve a voltage referenced to ground suitable for the TTL output interface logic.
On the other hand, when resistors are used, a satisfactorily uniform voltage referenced to ground can be achieved at the output since resistors do not provide a fixed voltage drop, but merely voltage division based upon current therethrough, but are unsatisfactory for the reason that they consume too much power and have a large time constant which is associated with actual and ambient capacitance.
Therefore, it is an object of the present invention to develop an interface between an ECL circuit and a TTL circuit, both of which operate from the same single supply voltage, which will translate from relative reference voltage levels near V.sub.BB, which is fundamentally referenced to the supply voltage, to TTL levels referenced to ground, and therefore not sensitive to V.sub.BB, yet which operates at the same high speed which characterizes ECL.
A further object is to provide a logic level converter which is insensitive to temperature.
Still another object is to devise an ECL to TTL logic level converter which from the standpoint of the TTL circuit appears to have the output impedance characteristics of a typical TTL circuit.
A further object is to devise an ECL to TTL logic level converter which is fully compatible with three state TTL logic, wherein one of the states is a disabled state; i.e., the circuit configuration and output impedance of the converter must readily interface with conventional three state circuit disabling circuitry.